(1) Field of the Invention
The present invention generally relates to fabrication of interconnect systems. More specifically, the present invention relates to fabrication of via plugs in interconnect systems that include low dielectric constant materials.
(2) Description of the Related Art
Modern integrated circuits are generally made up of a silicon substrate containing millions of active and passive devices including transistors, capacitors, and resistors. Such devices are initially isolated from one another, but are later interconnected together to form functional circuits. The quality of the interconnection of these devices drastically affects the performance and reliability of the fabricated integrated circuit. An interconnect system typically includes metal lines, spaced apart from each other, with dielectric layers therebetween that isolate the metal lines from one another. The metal lines typically interconnect the various active and passive devices residing in a silicon wafer to which the interconnect system is coupled.
Inherent in the structure of the interconnect system is a capacitance associated with the metal lines and the distance therebetween, i.e., inter-metal-line capacitance (hereinafter xe2x80x9ccapacitancexe2x80x9d). Decreasing this capacitance is desirable as several advantages can be achieved therefrom, such as reduced RC delay, reduced power dissipation, and reduced cross-talk between the metal lines. As the capacitance is inversely proportional to the distance between the metal lines, one way to reduce the capacitance formed between the lines of an interconnect system would be to increase the space between these lines. However, this option is not desirable because of limitations imposed by packing density.
However, as the capacitance of an interconnect system is also directly proportional with the dielectric constant of a dielectric disposed between these lines, a better way to reduce the capacitance of the interconnect system is to utilize a dielectric material with a low dielectric constant. Typically, interconnect systems use a dielectric material such as silicon dioxide (SiO2). The dielectric constant of SiO2 is approximately 4. Other dielectric materials that are used in interconnect systems include silicon oxyfluoride (SiOF), with a dielectric constant of 3.5 and below.
Incorporating dielectric materials with low dielectric constants in interconnect systems, however, is problematic. Low dielectric materials, such as organic polymers, may not adequately mechanically support the structure of the interconnect system as these materials are mechanically weak. Moreover, low dielectric constant materials such as organic polymers are vulnerable to certain processes involved in the fabrication of the interconnect system. For example, polymers have to withstand high temperatures and mechanical stresses at which the interconnect system is subjected. Also, polymers used in an interconnect system interact with photoresist solvents and developers used in the process of fabrication of the interconnect system. Moreover, polymers are vulnerable to exposure to photoresist solvents and developers as the polymers may dissolve in the solvents or developers and swell. Furthermore, polymers are vulnerable to oxygen plasma used in ashing.
An interconnect system typically utilizes via plugs made of tungsten (W), by way of non-limiting example, that interconnect the various layers of metal lines within the interconnect system. The vias plugs connect various layers of metal lines therebetween within the interconnect system. The process of connecting devices by interconnects is known as metallization. Current semiconductor fabrication processes typically utilize aluminum as metal for interconnects. Aluminum is superior to the other metals, such as copper, gold, and silver, for example, in terms of relative ease of deposition and patterning onto the semi-conductor substrate.
Once the via plugs are formed in an interconnect system, the via plugs are subjected to a process of chemical mechanical polishing (CMP), wherein a CMP slurry solution is used to polish and thereby planarize the outer parts of the via plugs. The CMP slurry solution, however, may cause deterioration or contamination of the polymer within which the via plugs are formed, if the interconnect system utilizes a polymer.
Low dielectric polymers suffer of other deficiencies that may discourage their incorporation in interconnects and formations of vias therein. The low dielectric polymer material may interact with via barrier and plug formation. Low dielectric constant polymer materials may interact in tungsten CMP processes. Also, low dielectric polymer materials have lower thermal stability (relative to silicon oxides).
With continued device scaling technology, it becomes more important to both reduce and control the interconnect thermal budget in processing. High temperature processing, after device formation, may have an adverse effect in transistor performance. Once the devices have been created, it is desirable to create the interconnects as low as possible processing temperature history. Typically, the photoresist is stripped at a temperature that may exceed 200 to 420 degrees Celsius when oxygen plasma or a microwave discharge is used.
It is desirable to provide an interconnect system that may accommodate the above-mentioned shortcomings of polymers or materials similar thereto.
The present invention provides a method for fabricating an interconnect system. A low dielectric constant layer (LDCL) is formed onto a substrate. A hard mask is formed onto the LDCL. A patterning material is formed onto the hard mask. The patterning material is via patterned. A via pattern of the patterning material is transferred to the hard mask. The patterning material is stripped at a substantially low temperature. Vias are formed through the LCDL using a via pattern formed in the hard mask.